1. Field of the Invention
Embodiments of the invention relate to a multi-chip semiconductor memory device with a plurality of memory chips built into one package and a related method of selectively enabling a memory chip within the device.
2. Description of the Related Art
The demand for small and diverse mobile devices such as PDAs, 3G mobile phones, digital still cameras, etc., has long been met by increasing the integration density and therefore reducing the size of the constituent components of semiconductor devices. However, continued reduction in the size of the constituent components in order to achieve even higher integration densities for contemporary semiconductor devices becomes increasingly difficult and is characterized by high cost and large amounts of development time. Accordingly, multi-chip packaging technology has recently been used in such mobile applications as an alternative to the use of increasingly dense semiconductor devices. A multi-chip package generally comprises several chips (e.g., memory chips, such as NOR flash memory chips, NAND flash memory chips, SRAM chips, UtRAM chips, etc.) mounted in a single package. In general, a multi-chip package has a structure in which two, four, or more homogeneous memory chips are vertically stacked one on top of the other. Thus, semiconductor devices formed using multi-chip package technology can reduce the semiconductor device mounting area within a host device by 50% or more, as compared with the use of separate semiconductor devices.
However, the presence of multiple chips within a multi-chip package results in the use of numerous pins (e.g., address pins, control pins, data I/O pins, etc.). This “high pin count” makes it difficult to construct a multi-chip package system. To address this problem, a plurality of memory chips in the multi-chip package may be arranged to share external pins. Unfortunately, the sharing of external pins by a plurality of memory chips within a multi-chip package generally precludes the use of a chip selection function.
FIG. 1 is a schematic diagram of a conventional multi-chip package, i.e., a dual die package (DDP) comprising a stacked arrangement of two homogenous chips in a single package. FIG. 2 is a timing diagram illustrating an operation of the conventional multi-chip package shown in FIG. 1.
Referring to FIG. 1, semiconductor chips 10 and 20 (which may be, for example, NOR flash memory chips, NAND flash memory chips, SRAM chips, UtRAM chips, etc.) are mounted in one package. An external chip enable signal nCEx activates semiconductor chips 10 and 20 for operation. In this case, although only one semiconductor chip will actually operate after the given external chip enable signal nCEx, both of semiconductor chips 10 and 20 are activated. Although it is not required to operate, the “not-to-be-selected” semiconductor chip nonetheless is still activated and dissipates power accordingly. A method of effectively avoiding this circumstance and thereby reducing the power dissipation of a multi-chip semiconductor package would be beneficial.